Altera Arria V Avalon-MM - Manual (Page 138)

According to the PCI Express Base Specification, if
MSI_enable
=0 and the
Disable Legacy Interrupt
bit
=1 in the Configuration Space
Command
register (0x004), the Hard IP should not send legacy interrupt
messages when an interrupt is generated.
9-22 Interrupt Handler Block
UG-01105_avmm
2014.12.15
Altera Corporation IP Core Architecture
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