Qsys system design for pci express – Altera Arria V Avalon-MM User Manual
Page 12
Getting Started with the Avalon‑MM Arria V
Hard IP for PCI Express
2
2014.12.15
UG-01105_avmm
You can download a design example for the Avalon-MM Arria V Hard IP for PCI Express from the
<install_dir>/ip/altera/altera_pcie/altera_pcie-<dev>_hip_avmm/example_designs
directory. This walkthrough
uses the a Gen1 x4 Endpoint, ep_g1x4.qsys.
The design examples contain the following components:
• Avalon-MM Arria V Hard IP for PCI Express IP core
• On-Chip memory
• DMA controller
• Transceiver Reconfiguration Controller
• Two Avalon-MM pipeline bridges
Figure 2-1: Qsys Generated Endpoint
Transaction,
Data Link,
and PHY
Layers
O n-C hip
Memory
DMA
Qsys System Design for PCI Express
PCI Express
Link
PCI
Express
Avalon-MM
Bridge
In
ter
connec
t
Avalon-MM Hard IP for PCI Express
Transceiver
Reconfiguration
Controller
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