Altera Arria V Avalon-MM - Manual (Page 149)

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardware
should help you determine the root cause. You can use the following tools to provide hardware visibility:
• SignalTap II Embedded Logic Analyzer
• Third-party PCIe analyzer
You can use SignalTap II Embedded Logic Analyzer to diagnose the LTSSM state transitions that are
occurring on the PIPE interface. The
ltssmstate[4:0]
bus encodes the status of LTSSM. The LTSSM
state machine reflects the Physical Layer’s progress through the link training process. For a complete
description of the states these signals encode, refer to Status, Link Training and Reset Signals. When link
training completes successfully and the link is up, the LTSSM should remain stable in the L0 state. When
link issues occur, you can monitor
ltssmstate[4:0]
to determine the cause.
Related Information
Reset
Setting Up Simulation
Changing the simulation parameters reduces simulation time and provides greater visibility.
Changing Between Serial and PIPE Simulation
By default, the Altera testbench runs a serial simulation. You can change between serial and PIPE
simulation by editing the top-level testbench file.
The
hip_ctrl_simu_mode_pipe
signal and
enable_pipe32_sim_hwtcl
parameter, specify serial or PIPE
simulation. When both are set to 1'b0, the simulation runs in serial mode. When both are set to 1'b1, the
simulation runs in PIPE mode. Complete the following steps to enable PIPE simulation. These steps
assume that the actual testbench in Gen1 x4 with an Avalon-MM 64-bit interface.
1. In the top-level testbench, which is
<working_dir>/<variant>/testbench/<variant>_tb/simulation/<variant>_
tb.v , change the signal,
hip_ctrl_simu_mode_pipe
to 1'b1 as shown:
pcie_de_gen1_x4_ast64 pcie_de_gen1_x4_ast64_x_inst (.dut_hip_ctrl_simu_mode_pipe
( 1'b1 ),
2. In the top-level HDL module for the Hard IP which is <working_dir>/<variant>/testbench/<variant>_tb/
simulation/submodules/<variant>.v change the parameter
enable_pipe32_sim_hwtcl
parameter to 1'b1
as shown:
altpcie_<dev>_hip_ast_hwtcl #( .enable_pipe32_sim_hwtcl ( 1 ),
Using the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater visibility.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory,
<work_dir>/<variant>/testbench/<variant>_tb/simulation
2. Open
<variant>_tb.v .
3. Search for the string,
serial_sim_hwtcl
. Set the value of this parameter to 0 if it is 1.
4. Save
<variant>_tb.v .
13-2 Setting Up Simulation
UG-01105_avmm
2014.12.15
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