Altera Arria V Avalon-MM - Manual (Page 42)

Signal Direction Description
int_status[3:0] Output These signals drive legacy interrupts to the Application Layer as
follows:
• int_status[0]: interrupt signal A
• int_status[1]: interrupt signal B
• int_status[2]: interrupt signal C
• int_status[3]: interrupt signal D
ko_cpl_spc_data[11:0] Output The Application Layer can use this signal to build circuitry to
prevent RX buffer overflow for completion data. Endpoints must
advertise infinite space for completion data; however, RX buffer
space is finite.
ko_cpl_spc_data
is a static signal that reflects the
total number of 16 byte completion data units that can be stored
in the completion RX buffer.
ko_cpl_spc_
header[7:0]
Output The Application Layer can use this signal to build circuitry to
prevent RX buffer overflow for completion headers. Endpoints
must advertise infinite space for completion headers; however,
RX buffer space is finite.
ko_cpl_spc_header
is a static signal
that indicates the total number of completion headers that can be
stored in the RX buffer.
l2_exit Output L2 exit. This signal is active low and otherwise remains high. It is
asserted for one cycle (changing value from 1 to 0 and back to 1)
after the LTSSM transitions from l2.idle to detect. When this
pulse is asserted, the Application Layer should generate an
internal reset signal that is asserted for at least 32 cycles.
lane_act[3:0]
Output Lane Active Mode: This signal indicates the number of lanes that
configured during link training. The following encodings are
defined:
• 4’b0001: 1 lane
• 4’b0010: 2 lanes
• 4’b0100: 4 lanes
• 4’b1000: 8 lanes
ltssmstate[4:0] Output LTSSM state: The LTSSM state machine encoding defines the
following states:
• 00000: Detect.Quiet
• 00001: Detect.Active
• 00010: Polling.Active
• 00011: Polling.Compliance
• 00100: Polling.Configuration
• 00101: Polling.Speed
4-12 Hard IP Status
UG-01105_avmm
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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