Altera Arria V Avalon-MM - Manual (Page 163)

Date Version Changes Made
• Added definition of
nreset_status
for variants using the
Avalon-MM interface.
• In Transaction Layer Routing Rules and Programming Model for
Avalon-MM Root Port , added the fact that Type 0 Configuration
Requests sent to the Root Port are not filtered by the device
number. Application Layer software must filter out requests for
device number greater than 0.
• Added Recommended Reset Sequence to Avoid Link Training Issues
to the Debugging chapter.
• Added limitation for
RxmIrq_<n>_i[<m>:0]
when interrupts are
received on consecutive cycles.
• Updated timing diagram for
tl_cfg_ctl
.
• Removed I/O Read Request and I/O Write Requests from TLPs
supported for Avalon-MM interface.
• Added note that the LTSSM interface can be used for SignalTap
debugging.
• Added restriction on the use of dynamic transceiver reconfigura‐
tion when CvP is enabled.
2014.05.06 13.0
Made the following changes:
• Timing models are now final.
• Added instructions for running the Single Dword variant.
• Corrected definition of
test_in[4:1]
. This vector must be set to
4’b0100.
• Corrected connection for
mgmt_clk_clk
in Figure 3-2.
• Corrected definition of
nPERSTL*
. The device has 1
nPERSTL*
pin
for each instance of the Hard IP for PCI Express in the device.
• Corrected feature comparison table in Datasheet chapter. The
Avalon-MM Hard IP for PCI Express IP Core does not support
legacy endpoints.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the following table.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [email protected]
C-4 How to Contact Altera
UG-01105_avmm
2014.08.18
Altera Corporation Additional Information
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