Altera 100G Development Kit, Stratix V GX Edition User Manual

Page 21

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Chapter 2: Board Components

2–13

MAX II CPLD EPM2210 System Controller

August 2012

Altera Corporation

100G Development Kit, Stratix V GX Edition

Reference Manual

M3

FACTORY

2.5-V

Push button to load factory image into the FPGA

M4

FACTORY_POF

2.5-V

LED to Indicate that factory Programmer Object File (.pof)
is loaded into the FPGA

V15

FACTORY_REQUEST

1.5-V

On-board USB-Blaster II request to send FACTORY
command

R13

FACTORY_STATUS

1.5-V

On-board USB-Blaster II FACTORY command status

A9

FLASH_ADVN

2.5-V

AE34

FSM bus flash address valid

D9

FLASH_CEN

2.5-V

AD14

FSM bus flash chip enable

E9

FLASH_OEN

2.5-V

AV8

FSM bus flash output enable

B9

FLASH_RDYBSYN

2.5-V

AU20

FSM bus flash ready

F9

FLASH_RESETN

2.5-V

AE32

FSM bus flash reset

A8

FLASH_WEN

2.5-V

AJ11

FSM bus flash write enable

B15

FPGA_CONF_DONE

2.5-V

AH9

FPGA configuration done

A15

FPGA_CONFIGN

2.5-V

AM38

Initiates new image to the FPGA

B18

FPGA_DATA0

2.5-V

BB38

FPGA configuration data

D14

FPGA_DATA1

2.5-V

BD38

FPGA configuration data

A17

FPGA_DATA2

2.5-V

BC39

FPGA configuration data

E13

FPGA_DATA3

2.5-V

BD37

FPGA configuration data

B16

FPGA_DATA4

2.5-V

BC38

FPGA configuration data

D13

FPGA_DATA5

2.5-V

AR37

FPGA configuration data

C15

FPGA_DATA6

2.5-V

AP37

FPGA configuration data

F12

FPGA_DATA7

2.5-V

AN39

FPGA configuration data

C14

FPGA_DCLK

2.5-V

AG36

FPGA configuration clock

R4

FPGA_JTAG_TCK

2.5-V

AL34

FPGA on-board JTAG chain clock

M7

FPGA_JTAG_TDO

2.5-V

AL36

FPGA on-board JTAG chain data out

E12

FPGA_STATUSN

2.5-V

AL8

FPGA configuration error

E11

FSM_A1

2.5-V

AR10

FSM bus flash address

B14

FSM_A2

2.5-V

AJ10

FSM bus flash address

B13

FSM_A3

2.5-V

AV20

FSM bus flash address

A12

FSM_A4

2.5-V

AN37

FSM bus flash address

A13

FSM_A5

2.5-V

BD7

FSM bus flash address

C13

FSM_A6

2.5-V

AL12

FSM bus flash address

C12

FSM_A7

2.5-V

AJ34

FSM bus flash address

D10

FSM_A8

2.5-V

AR11

FSM bus flash address

A7

FSM_A9

2.5-V

BD34

FSM bus flash address

B6

FSM_A10

2.5-V

AG19

FSM bus flash address

B7

FSM_A11

2.5-V

AW11

FSM bus flash address

C7

FSM_A12

2.5-V

AT11

FSM bus flash address

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference

(U59)

Schematic Signal

Name

I/O

Standard

Stratix V GX

Device Pin

Number

Pin Description

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