Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 68)

2–60 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
Table 2–36 lists the QDR II interface component reference and manufacturing
information.
Gigabit Ethernet Interface
The Stratix V GX development board incorporates a triple speed 10/100/1000 Base-T
Ethernet RGMII interface.
The implementation uses an auto-negotiating Marvell 88E1111 Ethernet PHY (U50)
with an RGMII interface to the FPGA (using Altera Triple-Speed Ethernet MegaCore
MAC function) and to a RJ-45 connector (J57) with internal magnetics that can be used
for driving copper lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA and Marvell 88E1111 PHY.
F2 QDR2B_Q12 1.5-V HSTL AM16 Read data bus
G3 QDR2B_Q13 1.5-V HSTL AL16 Read data bus
K3 QDR2B_Q14 1.5-V HSTL AL15 Read data bus
L2 QDR2B_Q15 1.5-V HSTL AL14 Read data bus
N3 QDR2B_Q16 1.5-V HSTL AJ13 Read data bus
P3 QDR2B_Q17 1.5-V HSTL AH13 Read data bus
A8 QDR2B_RPSN 1.5-V HSTL AV17 Read port select
A4 QDR2B_WPSN 1.5-V HSTL AJ18 Write port select
Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description
Table 2–38. QDR II interface Component Reference And Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U40
4 M × 18-bit, 333 MHZ,
burst-of-2 QDR II device Cypress
Semiconductor Inc.
CY7C1512KV18-333BZXC www.cypress.com
U41
2 M × 36-bit, 333 MHZ,
burst-of-2 QDR II device Cypress
Semiconductor Inc.
CY7C1514KV18-333BZXC www.cypress.com
Figure 2–9. Ethernet RGMII Interface
Stratix V GX
FPGA
RGMII
Interface
Marvell 88E1111
Ethernet PHY
TX/RX
RJ-45
Connector
Transformer
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T