Altera 100G Development Kit, Stratix V GX Edition User Manual

Page 59

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Chapter 2: Board Components

2–51

Components and Interfaces

August 2012

Altera Corporation

100G Development Kit, Stratix V GX Edition

Reference Manual

H7

DDR3D_DQ7

1.5-V SSTL

A28

Data bus

D7

DDR3D_DQ8

1.5-V SSTL

F29

Data bus

C3

DDR3D_DQ9

1.5-V SSTL

G29

Data bus

C8

DDR3D_DQ10

1.5-V SSTL

G28

Data bus

C2

DDR3D_DQ11

1.5-V SSTL

F28

Data bus

A7

DDR3D_DQ12

1.5-V SSTL

J27

Data bus

A2

DDR3D_DQ13

1.5-V SSTL

H26

Data bus

B8

DDR3D_DQ14

1.5-V SSTL

H28

Data bus

A3

DDR3D_DQ15

1.5-V SSTL

J28

Data bus

E3

DDR3D_DQ16

1.5-V SSTL

V25

Data bus

F7

DDR3D_DQ17

1.5-V SSTL

T26

Data bus

F2

DDR3D_DQ18

1.5-V SSTL

V26

Data bus

F8

DDR3D_DQ19

1.5-V SSTL

T25

Data bus

H3

DDR3D_DQ20

1.5-V SSTL

N25

Data bus

H8

DDR3D_DQ21

1.5-V SSTL

U27

Data bus

G2

DDR3D_DQ22

1.5-V SSTL

U26

Data bus

H7

DDR3D_DQ23

1.5-V SSTL

M25

Data bus

D7

DDR3D_DQ24

1.5-V SSTL

L26

Data bus

C3

DDR3D_DQ25

1.5-V SSTL

M28

Data bus

C8

DDR3D_DQ26

1.5-V SSTL

M27

Data bus

C2

DDR3D_DQ27

1.5-V SSTL

N28

Data bus

A7

DDR3D_DQ28

1.5-V SSTL

P26

Data bus

A2

DDR3D_DQ29

1.5-V SSTL

P27

Data bus

B8

DDR3D_DQ30

1.5-V SSTL

N26

Data bus

A3

DDR3D_DQ31

1.5-V SSTL

P29

Data bus

F3

DDR3D_DQS_P0

1.5-V SSTL

F26

Data strobe P byte lane 0

G3

DDR3D_DQS_N0

1.5-V SSTL

E27

Data strobe N byte lane 0

C7

DDR3D_DQS_P1

1.5-V SSTL

H27

Data strobe P byte lane 1

B7

DDR3D_DQS_N1

1.5-V SSTL

G26

Data strobe N byte lane 1

F3

DDR3D_DQS_P2

1.5-V SSTL

R25

Data strobe P byte lane 2

G3

DDR3D_DQS_N2

1.5-V SSTL

P25

Data strobe N byte lane 2

C7

DDR3D_DQS_P3

1.5-V SSTL

L27

Data strobe P byte lane 3

B7

DDR3D_DQS_N3

1.5-V SSTL

K27

Data strobe N byte lane 3

K1

DDR3D_ODT

1.5-V SSTL

A23

On-die termination

J3

DDR3D_RASN

1.5-V SSTL

E23

Row address select

T2

DDR3D_RSTN

1.5-V SSTL

D26

Reset

L3

DDR3D_WEN

1.5-V SSTL

E24

Write enable

DDR3 Port E Interface (U28, U35)

N3

DDR3E_A0

1.5-V SSTL

P28

Address bus

Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 11)

Board

Reference

Schematic Signal

Name

I/O Standard

Stratix V GX

Device Pin Number

Description

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