Chapter 5, 1 general, 2 board description – Nortel Networks DCT1900 User Manual

Page 173

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Technical Product Manual - DCT1900

Installation Instructions, Central Processing Unit (CPU) – REX-BRD0004 or 2/ROFNB 157 19/2

Install-DCT1900/R8/mw

5-1

© 2000-2005

C

HAPTER

5

Central Processing Unit (CPU) – REX-BRD0004 or 2/ROFNB 157 19/2

5.1

General

Maintenance
The CPU contains the following field–exchangeable parts (see Figure 5–4):

z

CPU Firmware (Mobility) - RYS 105 447

z

CPU Firmware (Standalone) - RYS 105 657

z

CPU Firmware, Poll Processor - REX-SW0014 or RYS 105 663

z

Sync FPGA (Field Programmable Gate Array) - RYSNB 101 24

z

Lithium Battery (type DL2032)

The CPU firmware is delivered as a separate item.

The lithium battery is a back-up power supply for the Real Time Clock (RTC) on the CPU board.
The RTC supplies the system date (year, month, day) and time (hours, minutes, seconds). If the
lithium battery dies, the system will require UTAM activation whenever the CPU power is cycled
unless it has been initialized as a non-UTAM system.

5.2

Board Description

Functionality
The CPU board is used in both a Standalone (SA) system and in a Mobility Server (MS) system.
The firmware that is resident on the CPU board determines which type of system the board will
function in.

Firmware RYS 105 657 is for Standalone Systems
Firmware RYS 105 447 is for Mobility Server Systems

Synchronization
If the CPU resides in a system that is part of multiple system configuration, PWT interface and
frame synchronization is required. When the PWT air interface is synchronized, efficient use of
the network capacity and seamless handovers between systems are possible when the coverage
areas overlap. To achieve PWT air interface synchronization in a multiple system configuration,
the respective CPUs (responsible for the frame timing) have to be in sync. CPUs are
synchronized using a master/slave concept, where one master CPU supplies a synchronization
signal to a number of slave CPUs. A slave CPU can act as a master for a further three slave
CPUs, thus creating a multi level star network with a maximum of two levels, see Figure 5-1.

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