Texas Instruments TMS320C64x DSP - Manual (Page 110)

Capturing Data in TSI Capture Mode
Video Capture Port 3-48 SPRU629
6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if
needed to initiate an interrupt, based on STC absolute time.
7) Write to TSITICKS if an interrupt is desired every x cycles of STC.
8) Write to VPCTL to select TSI capture operation (TSI = 1).
9) Write to VPIE to enable overrun (COVRA) and capture complete (CCMPA)
interrupts, if desired.
10) Write to VCACTL to set capture mode (CMODE = 010).
11) Set VCEN bit in VCACTL to enable capture.
12) Capture begins on the first VCLKINA rising edge when CAPENA and
PACSTRT are valid. A DMA event is generated as triggered by
VCATHRLD1. When the entire packet has been captured
(DCOUNT = VCYSTOP and VCXSTOP combined value), the FRMC bit
in VCASTAT is set causing the CCMPx bit in VPIS to be set. This gener-
ates a DSP interrupt, if CCMPx is enabled in VPIE.
13) If continuous capture is enabled, the video port begins capturing again on
the next VCLKINA rising edge when CAPENA and PACSTRT are valid. If
noncontinuous capture is enabled, the next data packet is captured during
which the DSP must clear the FRMC bit or further capture is disabled. If
single frame capture is enabled, capture is disabled until the DSP clears
the FRMC bit.
3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx
bit in VPIE enables overrun interrupt).
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it
should reconfigure DMA channel settings. The DMA channel must be reconfi-
gured for capture of the next frame since the current frame transfer failed. Set-
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the
channel. As long as the BLKCAP bit is set, the video capture channel ignores
the incoming data but the internal data counter continues counting.
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing
the BLKCAP bit takes effect on the next PACSTRT. (DMA events are still going
to be blocked in the TSI packet in which the BLKCAP bit is cleared.)