Texas Instruments TMS320C64x DSP - Manual (Page 205)

Video Display Registers
Video Display Port 4-60 SPRU629
4.12.3 Video Display Frame Size Register (VDFRMSZ)
The video display frame size register (VDFRMSZ) sets the display channel
frame size by setting the ending values for the frame line counter (FLCOUNT)
and the frame pixel counter (FPCOUNT). The VDFRMSZ is shown in
Figure 4–41 and described in Table 4–8.
The FPCOUNT starts at 0 and counts to FRMWIDTH – 1 before restarting. The
FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting.
Figure 4–41. Video Display Frame Size Register (VDFRMSZ)
31 28 27 16
Reserved FRMHEIGHT
R-0 R/W-0
15 12 11 0
Reserved FRMWIDTH
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–8. Video Display Frame Size Register (VDFRMSZ) Field Descriptions
Bit field † symval † Value Description
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
27–16 FRMHEIGHT OF(value) 0–FFFh Defines the total number of lines per frame. The number is
the ending value of the frame line counter (FLCOUNT).
For BT.656 operation, the FRMHIGHT is set to 525
(525/60 operation) or 625 (625/50 operation).
15–12 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
11–0 FRMWIDTH OF(value) 0–FFFh Defines the total number of pixels per line including blanking.
The number is the frame pixel counter (FPCOUNT) ending
value + 1.
For BT.656 operation, the FRMWIDTH is typically 858 or
864.
† For CSL implementation, use the notation VP_VDFRMSZ_field_symval