Texas Instruments TMS320C64x DSP - Manual (Page 287)

Example 2: Noncontinuous Frame Display for 525/60 Format
A-11 Video Port Configuration Examples SPRU629
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */
/* Define vertical blanking bit(VD_VBITn) reg values */
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */
#define VD_VBIT_SET1 1 /* first line with an EAV with V=1 */
/* indicating the start of Field1 */
/* vertical blanking */
#define VD_VBIT_CLR1 20 /* first line with an EAV with V=0 */
/* indicating the start of Field1 */
/* active display */
#define VD_VBLNK1_SIZE (VD_VBIT_CLR1 – VD_VBIT_SET1) /* 19 lines */
#define VD_VBIT_SET2 264 /* first line with an EAV with V=1 */
/* indicating the start of Field2 */
/* vertical blanking */
#define VD_VBIT_CLR2 283 /* first line with an EAV with V=0 */
/* indicating the start of Field2 */
/* active display */
#define VD_VBLNK2_SIZE (VD_VBIT_CLR2 – VD_VBIT_SET2) /* 19 lines */
/* –––––––––––– */
/* Field timing */
/* –––––––––––– */
#define VD_FIELD1_XSTART 720 /* pixel on the first line of */
/* Field1 on which FLD ouput */
/* is de–asserted */
#define VD_FIELD1_YSTART 1 /* line on which FLD is de–asserted */
#define VD_FIELD1_XSTART 360 /* pixel on the first line of */
/* Field1 on which FLD ouput */
/* is asserted */
#define VD_FIELD1_YSTART 263 /* line on which FLD is asserted */
/* –––––––––––––––––––––––––––––––––––– */
/* Define field bit(VD_FBIT) reg values */
/* –––––––––––––––––––––––––––––––––––– */
#define VD_FBIT_CLR 4 /* first line with an EAV with F=0 */
/* indicating Field 1 display */
#define VD_FBIT_SET 266 /* first line with an EAV with F=1 */
/* indicating Field 2 display */
/* –––––––––––––––––––––––––––––––– */
/* Define horzontal synchronization */
/* –––––––––––––––––––––––––––––––– */
#define VD_HSYNC_START 736
#define VD_HSYNC_STOP 800
/* –––––––––––––––––––––––––––––––––––––––––– */
/* Define vertical synchronization for field1 */
/* –––––––––––––––––––––––––––––––––––––––––– */
#define VD_VSYNC_XSTART1 720
#define VD_VSYNC_YSTART1 4
#define VD_VSYNC_XSTOP1 720
#define VD_VSYNC_YSTOP1 7