Texas Instruments TMS320C64x DSP - Manual (Page 270)

Interface
6-3 VCXO Interpolated Control Port SPRU629
6.2 Interface
The pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os).
Table 6–1. VIC Port Interface Signals
VIC Port Signal Direction Description
VCTL Output VCXO control
STCLK Input System time clock
6.3 Operational Details
Synchronization is an important aspect of decoding and presenting data in
real-time digital data delivery systems. This is addressed in the MPEG trans-
port packets by transmitting timing information in the adaptation fields of
selected data packets. This serves as a reference for timing comparison in the
receiving system. A sample of the 27-MHz clock, the program clock reference
(PCR) header is shown in Figure 6–2, is transmitted within the bit stream,
which indicates the expected time at the completion of reading the field from
the bit stream at the transport decoder. The sample is a 42-bit field, 9 bits cycle
from 0 to 299 at 27 MHz, while the other 33-bit field is incremented by 1 each
time the 9-bit field reaches a value of 299. The transport data packets are in
sync with the server system clock.
Figure 6–2. Program Clock Reference (PCR) Header Format
47 15 14 9 8 0
PCR Reserved PCR extension
The video port in conjunction with the VIC port uses a combined hardware and
software solution to synchronize the transport system time clock (STC) with
the clock reference transmitted in the bitstream.
The video port maintains a hardware counter that counts the system time. The
counter is driven by system time clock (STCLK) input driven by an external
VCXO, controlled by the VIC port.
On reception of a packet, the video port captures a snapshot of the counter.
Software uses this timestamp to determine the deviation of the system time
clock from the server clock, and drives VCTL output of the VIC port to keep it
synchronized.
Interface / Operational Details