Texas Instruments TMS320C64x DSP User Manual
Page 209
Video Display Registers
Video Display Port
4-64
SPRU629
4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
The video display field 1 vertical blanking end register (VDVBLKE1) controls
the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4–44
and described in Table 4–11.
In raw data mode, VBLNK is deasserted whenever the frame line counter
(FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT)
is equal to VBLNKXSTOP1 (this is shown in Figure 4–6, page 4-7).
In BT.656 and Y/C mode, VBLNK is deasserted whenever
FLCOUNT = VBLNKYSTOP1 and FPCOUNT = VBLNKXSTOP1. This
VBLNK output control is completely independent of the timing control codes.
The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.
Figure 4–44. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
31
28
27
16
Reserved
VBLNKYSTOP1
R-0
R/W-0
15
12
11
0
Reserved
VBLNKXSTOP1
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset