Texas Instruments TMS320C64x DSP - Manual (Page 211)

Video Display Registers
Video Display Port 4-66 SPRU629
Figure 4–45. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
31 28 27 16
Reserved VBLNKYSTART2
R-0 R/W-0
15 12 11 0
Reserved VBLNKXSTART2
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
Field Descriptions
Description
Bit field † symval † Value BT.656 and Y/C Mode Raw Data Mode
31–28 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
27–16 VBLNKYSTART2 OF(value) 0–FFFh Specifies the line (in
FLCOUNT) where
VBLNK active edge
occurs for field 2. Does
not affect EAV/SAV V bit
operation. Specifies the line (in
FLCOUNT) where vertical
blanking begins (VBLNK
active edge) for field 2.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
11–0 VBLNKXSTART2 OF(value) 0–FFFh Specifies the pixel (in
FPCOUNT) where
VBLNK active edge
occurs for field 2. Specifies the pixel (in
FPCOUNT) where
vertical blanking begins
(VBLNK active edge) for
field 2.
† For CSL implementation, use the notation VP_VDVBLKS2_field_symval