Texas Instruments TMS320C64x DSP - Manual (Page 199)

Video Display Registers
Video Display Port 4-54 SPRU629
Table 4–6. Video Display Status Register (VDSTAT) Field Descriptions
Bit field † symval † Value Description
31 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
30 FRMD Frame displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
NONE 0 Complete frame has not been displayed.
DISPLAYED 1 Complete frame has been displayed.
29 F2D Field 2 displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
NONE 0 Field 2 has not been displayed.
DISPLAYED 1 Field 2 has been displayed.
28 F1D Field 1 displayed bit. Write 1 to clear the bit, a write of 0 has
no effect.
NONE 0 Field 1 has not been displayed.
DISPLAYED 1 Field 1 has been displayed.
27–16 VDYPOS OF(value) 0–FFFh Current frame line counter (FLCOUNT) value. Index of the
current line in the current field being displayed by the
module.
15–14 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
13 VBLNK Vertical blanking bit.
EMPTY 0 Video display is not in a vertical-blanking interval.
NOTEMPTY 1 Video display is in a vertical-blanking interval.
12 VDFLD VDFLD bit indicates which field is currently being displayed.
The VDFLD bit is updated at the start of the vertical blanking
interval of the next field.
FIELD1ACT 0 Field 1 is active.
FIELD2ACT 1 Field 2 is active.
11–0 VDXPOS OF(value) 0–FFFh Current frame pixel counter (FPCOUNT) value. Index of the
most recently output pixel.
† For CSL implementation, use the notation VD_VDSTAT_field_symval