Texas Instruments TMS320C64x DSP - Manual (Page 228)

Video Display Registers
4-83 Video Display Port SPRU629
4.12.21 Video Display Counter Reload Register (VDRELOAD)
When external horizontal or vertical synchronization are used, the video
display counter reload register (VDRELOAD) determines what values are
loaded into the counters when an external sync is activated. The VDRELOAD
is shown in Figure 4–59 and described in Table 4–26.
Figure 4–59. Video Display Counter Reload Register (VDRELOAD)
31 28 27 16
Reserved VRLD
R-0 R/W-0
15 12 11 0
CRLD HRLD
R/W-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–26. Video Display Counter Reload Register (VDRELOAD) Field Descriptions
Bit field † symval † Value Description
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
27–16 VRLD OF(value) 0–FFFh Value loaded into frame line counter (FLCOUNT) when
external VSYNC occurs.
15–12 CRLD OF(value) 0–Fh Value loaded into video clock counter (VCCOUNT) when
external HSYNC occurs.
11–0 HRLD OF(value) 0–FFFh Value loaded into frame pixel counter (FPCOUNT) when
external HSYNC occurs.
† For CSL implementation, use the notation VP_VDRELOAD_field_symval