Texas Instruments TMS320C64x DSP - Manual (Page 306)

Index
Index-10 SPRU629
video port FIFO 1-5
video port interrupt enable register (VPIE) 2-21
video port interrupt status register (VPIS) 2-24
video port peripheral control register (PCR) 5-4
video port peripheral identification register
(VPPID) 5-3
video port pin data clear register (PDCLR) 5-17
video port pin data input register (PDIN) 5-11
video port pin data output register (PDOUT) 5-13
video port pin data set register (PDSET) 5-15
video port pin direction register (PDIR) 5-8
video port pin function register (PFUNC) 5-6
video port pin interrupt clear register (PICLR) 5-25
video port pin interrupt enable register (PIEN) 5-19
video port pin interrupt polarity register
(PIPOL) 5-21
video port pin interrupt status register
(PISTAT) 5-23
video port pin mapping 1-13
video port status register (VPSTAT) 2-20
VIE bit 2-21
VIF1 bit
in VCxVINT 3-63
in VDVINT 4-88
VIF2 bit
in VCxVINT 3-63
in VDVINT 4-88
VINT1 bits
in VCxVINT 3-63
in VDVINT 4-88
VINT2 bits
in VCxVINT 3-63
in VDVINT 4-88
VINTA1 bit
in VPIE 2-21
in VPIS 2-24
VINTA2 bit
in VPIE 2-21
in VPIS 2-24
VINTB1 bit
in VPIE 2-21
in VPIS 2-24
VINTB2 bit
in VPIE 2-21
in VPIS 2-24
VPCTL 2-17
VPHLT bit 2-17
VPIE 2-21
VPIS 2-24
VPPID 5-3
VPRST bit 2-17
VPSTAT 2-20
VRLD bits 4-83
VRST bit
in VCACTL 3-53
in VCBCTL 3-68
VSYNCXSTART1 bits 4-79
VSYNCXSTART2 bits 4-81
VSYNCXSTOP1 bits 4-80
VSYNCXSTOP2 bits 4-82
VSYNCYSTART1 bits 4-79
VSYNCYSTART2 bits 4-81
VSYNCYSTOP1 bits 4-80
VSYNCYSTOP2 bits 4-82
VXS bit 4-55
Y
Y FIFO destination register A (YDSTA) 4-96
Y FIFO destination register B (YDSTB) 4-96
Y FIFO source register (YSRCx) 3-83
Y/C mode 3-12, 4-16
blanking codes 4-17
capture channels 3-12
capture selection 3-18
capturing video 3-44
displaying video 4-47
field and frame operation 3-17
FIFO overrun 3-45
FIFO packing 3-14
FIFO unpacking 4-17
image display 4-17
image window and capture 3-13
timing reference codes 3-12, 4-16
YDEFVAL bits 4-86
YDSTA 4-96
YDSTB 4-96
YSRCx 3-83