Texas Instruments TMS320C64x DSP - Manual (Page 28)

Video Port FIFO
1-11 Overview SPRU629
Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration
Buffer A (2560 bytes)
YDSTA
VDOUT[9–0]
64 8/10
Display FIFO A
Buffer B (2560 bytes)
YDSTB
VDOUT[19–10]
64 8/10
Display FIFO B
For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown
in Figure 1–9. The FIFO outputs data on VDOUT[19–0]. The FIFO has a single
read pointer and write register (YDSTA).
Figure 1–9. 16/20-Bit Raw Video Display FIFO Configuration
Data Buffer (5120 bytes)
YDSTA
VDOUT[19–0]
64 16/20
Display FIFO