Texas Instruments TMS320C64x DSP - Manual (Page 197)

Video Display Registers
Video Display Port 4-52 SPRU629
4.12 Video Display Registers
The registers for controlling the video display mode of operation are listed in
Table 4–5. See the device-specific datasheet for the memory address of these
registers.
Table 4–5. Video Display Control Registers
Acronym Register Name Section
VDSTAT Video Display Status Register 4.12.1
VDCTL Video Display Control Register 4.12.2
VDFRMSZ Video Display Frame Size Register 4.12.3
VDHBLNK Video Display Horizontal Blanking Register 4.12.4
VDVBLKS1 Video Display Field 1 Vertical Blanking Start Register 4.12.5
VDVBLKE1 Video Display Field 1 Vertical Blanking End Register 4.12.6
VDVBLKS2 Video Display Field 2 Vertical Blanking Start Register 4.12.7
VDVBLKE2 Video Display Field 2 Vertical Blanking End Register 4.12.8
VDIMGOFF1 Video Display Field 1 Image Offset Register 4.12.9
VDIMGSZ1 Video Display Field 1 Image Size Register 4.12.10
VDIMGOFF2 Video Display Field 2 Image Offset Register 4.12.11
VDIMGSZ2 Video Display Field 2 Image Size Register 4.12.12
VDFLDT1 Video Display Field 1 Timing Register 4.12.13
VDFLDT2 Video Display Field 2 Timing Register 4.12.14
VDTHRLD Video Display Threshold Register 4.12.15
VDHSYNC Video Display Horizontal Synchronization Register 4.12.16
VDVSYNS1 Video Display Field 1 Vertical Synchronization Start Register 4.12.17
VDVSYNE1 Video Display Field 1 Vertical Synchronization End Register 4.12.18
VDVSYNS2 Video Display Field 2 Vertical Synchronization Start Register 4.12.19
VDVSYNE2 Video Display Field 2 Vertical Synchronization End Register 4.12.20
VDRELOAD Video Display Counter Reload Register 4.12.21
VDDISPEVT Video Display Display Event Register 4.12.22
VDCLIP Video Display Clipping Register 4.12.23