Texas Instruments TMS320C64x DSP - Manual (Page 118)

Video Capture Registers
Video Capture Port 3-56 SPRU629
Table 3–15. Video Capture Channel A Control Register (VCACTL)
Field Descriptions (Continued)
Description
Bit TSI Mode Raw Data Mode BT.656 or Y/C Mode Value symval † field †
12 LFDE Long field detect enable bit.
DISABLE 0 Long field detect
is disabled. Not used. Not used.
ENABLE 1 Long field detect
is enabled. Not used. Not used.
11 SFDE Short field detect enable bit.
DISABLE 0 Short field detect
is disabled. Not used. Not used.
ENABLE 1 Short field detect
is enabled. Not used. Not used.
10 RESMPL Chroma resampling enable bit.
DISABLE 0 Chroma resampling is
disabled. Not used. Not used.
ENABLE 1 Chroma is horizontally
resampled from
4:2:2 co-sited to
4:2:0 interspersed
before saving to
chroma buffers. Not used. Not used.
9 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
8 SCALE Scaling select bit.
NONE 0 No scaling Not used. Not used.
HALF 1
½
scaling Not used. Not used.
7 CON ‡ Continuous capture enable bit.
DISABLE 0 Continuous capture is disabled.
ENABLE 1 Continuous capture is enabled.
† For CSL implementation, use the notation VP_VCACTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.