Texas Instruments TMS320C64x DSP - Manual (Page 225)

Video Display Registers
Video Display Port 4-80 SPRU629
4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
The video display field 1 vertical synchronization end register (VDVSYNE1)
controls the end of vertical synchronization in field 1. The VDVSYNE1 is
shown in Figure 4–56 and described in Table 4–23.
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
The VSYNC signal is deasserted whenever the frame line counter (FLCOUNT)
is equal to VSYNCYSTOP1 and the frame pixel counter (FPCOUNT) is equal
to VSYNCXSTOP1.
Figure 4–56. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
31 28 27 16
Reserved VSYNCYSTOP1
R-0 R/W-0
15 12 11 0
Reserved VSYNCXSTOP1
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
Field Descriptions
Bit field † symval † Value Description
31–28 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
27–16 VSYNCYSTOP1 OF(value) 0–FFFh Specifies the line where VSYNC is deasserted for
field 1.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
11–0 VSYNCXSTOP1 OF(value) 0–FFFh Specifies the pixel where VSYNC is deasserted in
field 1.
† For CSL implementation, use the notation VP_VDVSYNE1_field_symval