Texas Instruments TMS320C64x DSP User Manual
Page 80
BT.656 and Y/C Mode Field and Frame Operation
Video Capture Port
3-18
SPRU629
Table 3–6. BT.656 and Y/C Mode Capture Operation
VCxCTL Bit
CON
FRAME
CF2
CF1
Operation
0
0
0
0
Reserved
0
0
0
1
Noncontinuous field 1 capture. Capture only field 1. F1C is set after
field 1 capture and causes CCMPx to be set. The F1C bit must be
cleared by the DSP before capture can continue. (The DSP has the
entire field 2 time to clear F1C before next field 1 begins.) Can also be
used for single progressive frame capture. (The DSP has vertical
blanking time to clear F1C before next frame begins.)
0
0
1
0
Noncontinuous field 2 capture. Capture only field 2. F2C is set after
field 2 capture and causes CCMPx to be set. The F2C bit must be
cleared by the DSP before capture can continue. (The DSP has the
entire field 1 time to clear F2C before next field 2 begins.)
0
0
1
1
Noncontinuous field 1 and field 2 capture. Capture both fields. F1C is
set after field 1 capture and causes CCMPx to be set. The F1C bit must
be cleared by the DSP before another field 1 capture can occur. (The
DSP has the entire field 2 time to clear F1C before next field 1 begins.)
F2C is set after field 2 capture and causes CCMPx to be set. The F2C
bit must be cleared by the DSP before another field 2 capture can
occur. (The DSP has the entire field 1 time to clear F2C before next
field 2 begins.)
0
1
0
0
Noncontinuous frame capture. Capture both fields. FRMC is set after
field 2 capture and causes CCMPx to be set. Capture halts upon
completion of the next frame unless the FRMC bit is cleared. (The DSP
has the entire next frame time to clear FRMC.)
0
1
0
1
Noncontinuous progressive frame capture. Capture field 1. FRMC is set
after field 1 capture and causes CCMPx to be set. Capture halts upon
completion of the next frame unless the FRMC bit is cleared. (The DSP
has the entire next frame time to clear FRMC.)
0
1
1
0
Reserved
0
1
1
1
Single frame capture. Capture both fields. FRMC is set after field 2
capture and causes CCMPx to be set. Capture halts until the FRMC bit
is cleared. (The DSP has the field 2 to field 1 vertical blanking time to
clear FRMC.)
1
0
0
0
Reserved
1
0
0
1
Continuous field 1 capture. Capture only field 1. F1C is set after field 1
capture and causes CCMPx to be set (CCMPx interrupt can be
disabled). The video port continues capturing field 1 fields, regardless
of the state of F1C.