Texas Instruments TMS320C64x DSP - Manual (Page 132)

Video Capture Registers
Video Capture Port 3-70 SPRU629
Table 3–23. Video Capture Channel B Control Register (VCBCTL)
Field Descriptions (Continued)
Description
Bit TSI Mode Raw Data Mode BT.656 or Y/C Mode Value symval † field †
16 HRST HCOUNT reset method bit.
EAV 0 EAV or
VCTL1 active edge. Not used. Not used.
SAV 1 SAV or
VCTL1 inactive edge. Not used. Not used.
15 VCEN Video capture enable bit. Other bits in VCBCTL (except RSTCH
and BLKCAP bits) may only be changed when VCEN = 0.
DISABLE 0 Video capture is disabled.
ENABLE 1 Video capture is enabled.
14–13 PK10B 10-bit packing format select bit.
ZERO 0 Zero extend Zero extend Not used.
SIGN 1h Sign extend Sign extend Not used.
DENSEPK 2h Dense pack (zero
extend) Dense pack (zero
extend) Not used.
– 3h Reserved Reserved Not used.
12 LFDE Long field detect enable bit.
DISABLE 0 Long field detect
is disabled. Not used. Not used.
ENABLE 1 Long field detect
is enabled. Not used. Not used.
11 SFDE Short field detect enable bit.
DISABLE 0 Short field detect
is disabled. Not used. Not used.
ENABLE 1 Short field detect
is enabled. Not used. Not used.
† For CSL implementation, use the notation VP_VCBCTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.