Texas Instruments TMS320C64x DSP - Manual (Page 203)

Video Display Registers
Video Display Port 4-58 SPRU629
Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)
Bit
Description
Value symval † field † Bit Raw Data Mode BT.656 and Y/C Mode Value symval † field †
13 RGBX RGB extract enable bit.
DISABLE 0 Not used.
ENABLE 1 Not used. Perform ¾ FIFO unpacking.
12 RSYNC Second, synchronized raw data channel enable bit.
DISABLE 0 Not used. Second, synchronized raw data
channel is disabled.
ENABLE 1 Not used. Second, synchronized raw data
channel is enabled.
11 DVEN Default value enable bit.
BLANKING 0 Blanking value is output during
non-sourced active pixels. Not used.
DV 1 Default value is output during
non-sourced active pixels. Not used.
10 RESMPL Chroma resampling enable bit.
DISABLE 0 Chroma resampling is disabled. Not used.
ENABLE 1 Chroma is horizontally
resampled from 4:2:0
interspersed to 4:2:2 co-sited
before output. Not used.
9 Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
8 SCALE Scaling select bit.
NONE 0 No scaling Not used.
X2 1 2
×
scaling Not used.
7 CON ‡ Continuous display enable bit.
DISABLE 0 Continuous display is disabled.
ENABLE 1 Continuous display is enabled.
† For CSL implementation, use the notation VP_VDCTL_field_symval
‡ For complete encoding of these bits, see Table 4–4.