Texas Instruments TMS320C64x DSP - Manual (Page 215)

Video Display Registers
Video Display Port 4-70 SPRU629
4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)
The video display field 1 image size register (VDIMGSZ1) defines the field 1
image area and specifies the size of the displayed image within the active dis-
play. The VDIMGSZ1 is shown in Figure 4–48 and described in Table 4–15.
The image pixel counter (IPCOUNT) counts displayed image pixel output on
each of the displayed image. Displayed image pixel output stops when
IPCOUNT = IMGHSIZE1. The default output values or blanking values are
output for the remainder of the active line.
The image line counter (ILCOUNT) counts displayed image lines. Displayed
image output stops when ILCOUNT = IMGVSIZE1. The default output values
or blanking values are output for the remainder of the active field.
Figure 4–48. Video Display Field 1 Image Size Register (VDIMGSZ1)
31 28 27 16
Reserved IMGVSIZE1
R-0 R/W-0
15 12 11 0
Reserved IMGHSIZE1
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–15. Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions
Description
Bit field † symval † Value BT.656 and Y/C Mode Raw Data Mode
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
27–16 IMGVSIZE1 OF(value) 0–FFFh Specifies the display image height in lines.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
11–0 IMGHSIZE1 OF(value) 0–FFFh Specifies the display image
width in pixels. This number
must be even (the LSB is
treated as 0) Specifies the display image
width in pixels.
† For CSL implementation, use the notation VP_VDIMGSZ1_field_symval