3 sync signal generation – Texas Instruments TMS320C64x DSP User Manual
Page 152
Video Display Mode Selection
4-7
Video Display Port
SPRU629
Note that the signals can transition at any place along the video line (specified
by the XSTART and XSTOP bits of the appropriate registers). In this case,
VBLNK starts at horizontal count VBLNKXSTART2 = 429 on scan line
VBLNKYSTART2 = 263 (565/60 operation).
Figure 4–6. Vertical Blanking, Sync and Even/Odd Frame Signal Timing
FLCOUNT
VBLNK
VSYNC
FLCOUNT = VSYNCYSTOP1
FPCOUNT = VSYNCXSTOP1
263
264
265
18
19
20
5
6
7
266
282
283
284
524
525
1
2
3
4
5
267
268
269
270
FLD
FLCOUNT = VBLNKYSTOP1
FPCOUNT = VBLNKXSTOP1
FLCOUNT = VBLNKYSTART2
FPCOUNT = VBLNKXSTART2
FLCOUNT = VBLNKYSTOP2
FPCOUNT = VBLNKXSTOP2
FLCOUNT = VBLNKYSTART1
FPCOUNT = VBLNKXSTART1
FLCOUNT = VSYNCYSTART2
FPCOUNT = VSYNCXSTART2
FLCOUNT = VSYNCYSTART1
FPCOUNT = VSYNCXSTART1
FLCOUNT = VSYNCYSTOP2
FPCOUNT = VSYNCXSTOP2
FLCOUNT = FLD2YSTART
FPCOUNT = FLD2XSTART
FLCOUNT = FLD1YSTART
FPCOUNT = FLD1XSTART
One Frame
One Line
Field 2
Field 1
4.1.3
Sync Signal Generation
The video display module must generate a number of control signals for both
internal and external use. As seen in section 4.1.2, the HSYNC, HBLNK,
VSYNC, VBLNK, and FLD signals are generated directly from the pixel and
line counters and comparison registers. Several additional signals are also
generated indirectly for use in external control.
A composite blank (CBLNK) signal is generated as the logical-OR of the
HBLNK and VBLNK signals. A composite sync (CSYNC) signal is also gener-
ated as the logical-OR of the HSYNC and VSYNC signals. (This is not a true
analog CSYNC, which must include serration pulses during VSYNC and
equalization pulses during vertical front and back porch periods.) Finally, an
active video (AVID) signal is generated. AVID is the inverted CBLNK signal
indicating when active video data is being output.
Up to three of the eight sync signals may be output on VCTL1, VCTL2, and
VCTL3 as selected by the video display control register (VDCTL). Each signal
may be output in its noninverted or inverted form, as selected by the VCTnP
bits in the video port control register (VPCTL).