Texas Instruments TMS320C64x DSP - Manual (Page 17)

Tables
xvii Tables SPRU629
4–26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions 4-83 . . . . . . . . . . . .
4–27 Video Display Display Event Register (VDDISPEVT) Field Descriptions 4-84 . . . . . . . . . . . . .
4–28 Video Display Clipping Register (VDCLIP) Field Descriptions 4-85 . . . . . . . . . . . . . . . . . . . . . .
4–29 Video Display Default Display Value Register (VDDEFVAL) Field Descriptions 4-87 . . . . . . .
4–30 Video Display Vertical Interrupt Register (VDVINT) Field Descriptions 4-88 . . . . . . . . . . . . . . .
4–31 Video Display Field Bit Register (VDFBIT) Field Descriptions 4-89 . . . . . . . . . . . . . . . . . . . . . .
4–32 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions 4-91 . . . .
4–33 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions 4-93 . . . .
4–34 Video Display Register Recommended Values 4-94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–35 Video Display FIFO Registers 4-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–36 Video Display FIFO Registers Function 4-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Video Port Registers 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Video Port Peripheral Identification Register (VPPID) Field Descriptions 5-3 . . . . . . . . . . . . . .
5–3 Video Port Peripheral Control Register (PCR) Field Descriptions 5-5 . . . . . . . . . . . . . . . . . . . .
5–4 Video Port Pin Function Register (PFUNC) Field Descriptions 5-6 . . . . . . . . . . . . . . . . . . . . . . .
5–5 Video Port Pin Direction Register (PDIR) Field Descriptions 5-8 . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Video Port Pin Data Input Register (PDIN) Field Descriptions 5-12 . . . . . . . . . . . . . . . . . . . . . .
5–7 Video Port Pin Data Out Register (PDOUT) Field Descriptions 5-14 . . . . . . . . . . . . . . . . . . . . .
5–8 Video Port Pin Data Set Register (PDSET) Field Descriptions 5-16 . . . . . . . . . . . . . . . . . . . . . .
5–9 Video Port Pin Data Clear Register (PDCLR) Field Descriptions 5-18 . . . . . . . . . . . . . . . . . . . .
5–10 Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions 5-20 . . . . . . . . . . . . . . . . .
5–11 Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions 5-22 . . . . . . . . . . . . . . . .
5–12 Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions 5-24 . . . . . . . . . . . . . . . .
5–13 Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions 5-26 . . . . . . . . . . . . . . . . .
6–1 VIC Port Interface Signals 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Example Values for Interpolation Rate 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 VIC Port Registers 6-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 VIC Control Register (VICCTL) Field Descriptions 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 VIC Input Register (VICIN) Field Descriptions 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 VIC Clock Divider Register (VICDIV) Field Descriptions 6-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . .