Texas Instruments TMS320C64x DSP - Manual (Page 51)

Video Port Control Registers
Video Port 2-18 SPRU629
Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued)
Bit Description Value symval † field †
14 VPHLT Video port halt bit. This bit is set upon hardware or software
reset. The other VPCTL bits (except VPRST) can only be
changed when VPHLT is 1. VPHLT is cleared by writing a 1.
Writing 0 has no effect.
NONE 0
CLEAR 1
13–8 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
7 VCLK2P VCLK2 pin polarity bit. Has no effect in capture mode.
NONE 0
REVERSE 1 Inverts the VCLK2 output clock polarity in display mode.
6 VCT3P VCTL3 pin polarity. Does not affect GPIO operation. If VCTL3
pin is used as a FLD input on the video capture side, then the
VCTL3 polarity is not considered; the field inverse is controlled
by the FINV bit in the video capture channel x control register
(VCxCTL).
NONE 0
ACTIVELOW 1 Indicates the VCTL3 control signal (input or output) is active
low.
5 VCT2P VCTL2 pin polarity bit. Does not affect GPIO operation.
NONE 0
ACTIVELOW 1 Indicates the VCTL2 control signal (input or output) is active
low.
4 VCT1P VCTL1 pin polarity bit. Does not affect GPIO operation.
NONE 0
ACTIVELOW 1 Indicates the VCTL1 control signal (input or output) is active
low.
3 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
† For CSL implementation, use the notation VP_VPCTL_field_symval