Texas Instruments TMS320C64x DSP - Manual (Page 236)

Video Display Registers
4-91 Video Display Port SPRU629
Table 4–32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
Field Descriptions
Description
Bit field † symval † Value BT.656 and Y/C Mode Raw Data Mode
31–28 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
27–16 VBITCLR1 OF(value) 0–FFFh Specifies the first line with an EAV of
V = 0 indicating the start of field 1
active display. Not used.
15–12 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
11–0 VBITSET1 OF(value) 0–FFFh Specifies the first line with an EAV of
V = 1 indicating the start of field 1
vertical blanking. Not used.
† For CSL implementation, use the notation VP_VDVBIT1_field_symval