Rockwell Automation 1771-QA Stepper Positioning Assembly User Manual - Manual (Page 49)

3–27 Programming and Operation
Publication 1771-UM002A–EN–P – May 2000
Two consecutive data addresses must be used in bidirectional block
transfer. Both contain the I/O rack address of the stepper controller
module. For bidirectional operation, each data address word also
contains an enable bit; bit 16 for a write operation and bit 17 for a
read operation. When the PC processor searches the data addresses
in the timer/counter accumulated area of the data table, it finds two
consecutive data addresses both containing the same module address.
The read bit is set in one data address. The write bit is set in the
other. When the PC processor finds a match of the module address
and enable bit (read or write bit) for the desired direction of transfer,
it then locates the file address to which (or from which) the data will
be transferred. The file address is stored in a word 100
8
above the
corresponding data address.
A boundary word containing zeros should be entered in the data
table following the last block transfer data address. When the
processor sees this boundary word, it will terminate the block
transfer search routine so subsequent data table values cannot be
interpreted as rack, module group and slot numbers associated with
block transfer data addresses.
Block Length
The block length is the number of words transferred to or from the
stepper controller module. The module can receive up to 64 words
of a moveset block from the PC processor in one write block
transfer. It can transfer to the PC processor up to 10 words of status
in one read block transfer. These are the maximum (default) block
length values of the module. Only selected values as determined by
the size of the moveset block or status block, not exceeding the
default value, can be entered as the block length. The value of 00
must be used to set the block length for a read or write block transfer
to the default value (64 for a write operation or 10 for a read
operation).
Multiple Writes of Different Block Lengths to One Module
When two or more write block transfer instructions have a common
module address, careful programming is required to compensate for
the following possible situations:
During any program scan, the enable bit can be set or reset
alternately according to the true or false condition of the rungs
containing these instructions. The true or false status of the last rung
will govern whether the transfer will occur.