Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 37)

Chapter 2: Board Components 2–29
General User Input/Output
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
Single-Ended Clocks
The single-ended clock buffers are located near the 644-MHz clock. Each single-ended
clock buffer can use either a bench clock supplied to its SMA or the PLL clock from the
on-board external PLLs. Refer to
Table 2–12 on how to select between SMA or PLL
using the board settings DIP switch.
General User Input/Output
This section describes the user I/O interface to the FPGA and MAX II CPLD EPM2210
System Controller, including the push-buttons switches, user LEDs, user DIP
switches, and LCD. The I/O signals are connected between the FPGA and the MAX II
CPLD EPM2210 System Controller to enable I/O expansion when necessary.
The MAX II CPLD EPM2210 System Controller passes the I/Os from the FPGA to the
I/O elements connected on the MAX II CPLD.
Figure 2–10 shows the general user I/O connection.
User Push-Button Switches
The development board includes eight push-button switches for user-defined logic
input and one CPU reset. For information on the CPU reset push-button switch, refer
to
“Push-Button Switches” on page 2–21 .
Board references S1-S4 and S5-S8 are push-button switches that allow you to interact
with the MAX II CPLD device and the Stratix IV GT device. When the switch is
pressed and held down, the device pin is set to logic 0; when the switch is released,
the device pin is set to logic 1. There is no board-specific function for these general
user push-button switches.
Figure 2–10. General User I/O Connection
8 User DIP
5 User
Buttons
8 User
LEDs
MAX II CPLD
(U72)
Stratix IV GT
FPGA
(U44)
8 User DIP
4 User
Buttons
4 User
LEDs
MAX_STRATIX