Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 61)

Chapter 2: Board Components 2–53
Components and Interfaces
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
U29.R7, U28.R7 Address bus DDR3C_A11 U44.J28 —
U29.N7, U28.N7 Address bus DDR3C_A12 U44.E29 —
U29.M2, U28.M2 Bank address bus DDR3C_BA0 U44.L35 —
U29.N8, U28.N8 Bank address bus DDR3C_BA1 U44.M26 —
U29.M3, U28.M3 Bank address bus DDR3C_BA2 U44.L34 —
U29.K3, U28.K3 Column address select DDR3C_CASN U44.T30 —
U29.K7, U28.K7 Clock input N DDR3C_CK_N U44.H38 —
U29.J7, U28.J7 Clock input P DDR3C_CK_P U44.J38 —
U29.K9, U28.K9 Clock enable DDR3C_CKE U44.L29 —
U29.L2, U28.L2 Chip select DDR3C_CSN U44.F35 —
U28.E3 Data bus DDR3C_DQ0 U44.N27 —
U28.F7 Data bus DDR3C_DQ1 U44.P25 —
U28.F2 Data bus DDR3C_DQ2 U44.K26 —
U28.F8 Data bus DDR3C_DQ3 U44.T25 —
U28.H3 Data bus DDR3C_DQ4 U44.M27 —
U28.H8 Data bus DDR3C_DQ5 U44.R25 —
U28.G2 Data bus DDR3C_DQ6 U44.M28 —
U28.H7 Data bus DDR3C_DQ7 U44.N25 —
U28.D7 Data bus DDR3C_DQ8 U44.J29 —
U28.C3 Data bus DDR3C_DQ9 U44.H29 —
U28.C8 Data bus DDR3C_DQ10 U44.H26 —
U28.C2 Data bus DDR3C_DQ11 U44.F29 —
U28.A7 Data bus DDR3C_DQ12 U44.J27 —
U28.A2 Data bus DDR3C_DQ13 U44.G29 —
U28.B8 Data bus DDR3C_DQ14 U44.J26 —
U28.A3 Data bus DDR3C_DQ15 U44.G26 —
U29.E3 Data bus DDR3C_DQ16 U44.E28 —
U29.F7 Data bus DDR3C_DQ17 U44.D26 —
U29.F2 Data bus DDR3C_DQ18 U44.D29 —
U29.F8 Data bus DDR3C_DQ19 U44.F26 —
U29.H3 Data bus DDR3C_DQ20 U44.D28 —
U29.H8 Data bus DDR3C_DQ21 U44.E26 —
U29.G2 Data bus DDR3C_DQ22 U44.C29 —
U29.H7 Data bus DDR3C_DQ23 U44.D27 —
U29.D7 Data bus DDR3C_DQ24 U44.A28 —
U29.C3 Data bus DDR3C_DQ25 U44.B29 —
U29.C8 Data bus DDR3C_DQ26 U44.A27 —
U29.C2 Data bus DDR3C_DQ27 U44.A31 —
Table 2–37. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 8)
Board Reference Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections