Panasonic MN101C77C - Manual (Page 114)

Chapter 3 Interrupts
III - 20 Control Registers
■ External Interrupt 3 Control Register (IRQ3ICR)
The external interrupt 3 control register (IRQ3ICR) controls interrupt level of external interrupt 3, active
edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-5 External Interrupt 3 Control Register (IRQ3ICR : x'03FE5', R/W)
IRQ3
LV1
Interrupt level flag for external interrupt
IRQ3
LV0
0 1 2 4 5 6 7 3
(At reset : 0 0 0 - - - 0 0) IRQ3ICR
0
1
No interrupt request
External interrupt request flag
Interrupt request generated
IRQ3IE
IRQ3IR
0
1
Disable interrupt
External interrupt enable flag
Enable interrupt
IRQ3IE
0
1 Rising edge
External interrupt active edge flag
Falling edge
The CPU has interrupt levels from 0 to 3. These
flags set the interrupt level for interrupt requests
REDG3
IRQ3IR
IRQ3
- - -
LV1
IRQ3
LV0
REDG3