Panasonic MN101C77C - Manual (Page 481)

XV - 7
Chapter 15 A/D Converter
Control Registers
15-2-3 Data Buffers
„ A/D Conversion Data Storage Buffer 0 (ANBUF0)
The lower 2 bits from the result of A/D conversion are stored to this register.
„ A/D Conversion Data Storage Buffer 1 (ANBUF1)
The upper 8 bits from the result of A/D conversion are stored to this register.
Figure 15-2-4 A/D Conversion Data Buffer 0 (ANBUF0 : x'03FB3', R)
Figure 15-2-5 A/D Conversion Data Buffer 1 (ANBUF1 : x'03FB4', R)
0 1 2 4 5 6 7 3
ANBUF0 ANBUF07 ANBUF06
(At reset : X X - - - - - -)
0 1 2 4 5 6 7 3
ANBUF1 ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10
(At reset : X X X X X X X X)