Panasonic MN101C77C - Manual (Page 331)

XI - 5
Chapter 11 Serial Interface 0, 1
Overview
„ Serial Interface 1 Block Diagram
Figure 11-1-2 Serial Interface 1 Block Diagram
Reception shift register
SC1RIRQ
Start condition
generation circuit
3
IRQ control circuit
Clock control circuit
match Reception bit counter BUSY generation circuit
Received buffer
Transmission shift register
Parity bit control circuit
Start condition
detection circuit
MUX
M U X M U X
match
Break status receive monitor
Transmission buffer
SC1MD3
SC1MD2
SC1MD1
SC1MD0
Transmission bit counter
SC1TIRQ
0 7
SC1ERE SC1ORE SC1PEK SC1FEF
SC1RBSY SC1TBSY SC1REMP SC1TEMP
SC1IOM SC1CMD SC1SBIS SC1SBOS SC1SBTS SC1CKM
0 7
SC1MST
SC1BRKF SC1BRKE
SC1NPE SC1PM0 SC1PM1 SC1FM0 SC1FM1
0 7
1/8
sc1psc
(prescaler output)
SC1CE1 SC1STE SC1DIR
SC1LNG0 SC1LNG1 SC1LNG2
0 7
SC1CKM
SC1DIR
SC1STE
SC1CMD
SC1STE
Stop bit detection circuit
Overrun error detection
SC1FM0 SC1FM1
SC1NPE
SC1FM0 SC1FM1
SC1PM0 SC1PM1
SC1SBIS
SC1BRKE
Read/Write
SC1RDB
SC1TRB
RXBUF1
TXBUF1
SWAP MSB<->LSB
SC1REN SC1TRN
M U X
M U X
SB1IOM
SCISEL
SBI1A/P01 SBI1
B/P74
SBO1A/P00 SBO1B/P73
P O L
SC1CE1
SBT1A/P02
M U X
SC1SEL
SBT1B/P75
SCISBTS
SBO1B/P73
SC1SBOS
SBO1A/P00
M U X
SC1SEL
M U X
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