Panasonic MN101C77C - Manual (Page 263)

VII - 3
Chapter 7 16-bit Timer
Overview
7-1-2 Block Diagram
„ Timer 7 Block Diagram
Figure 7-1-1 Timer 7 Block Diagram
T7OC2IRQ
OVF
M U X M U X
1/2
R
TM7CL
TM7MD1(bp5)
M U X
TM7IO output / PWM7
reset
Match
RST
RST
TM7BCL
TM7BCH
M U X
4-bit prescaler
1/2
1
/2
1/4
S
1/16 1/4 1/2 1
M U X
0 7
TM7CK0 TM7CK1 TM7PS0 TM7PS1 TM7EN TM7CL
TM7MD1
Match
16-Bit preset register 1
TM7PR1L
TM7PR1H
Data Load signal
TM7OC1H
M U X
Read/Write
Read
TM7OC2H
Data Load signal
TM7PR2H
16-Bit output, compare register 2
TM7PR2L TM7OC2L TM7OC1L
Read/Write
R
e
ad
0 7
T7ICT0 T7ICT1
TM7MD2 TM7IRS1 TM7PWM TM7BCR T7PWMSL
T7ICEN
TM7IO input
fs
fosc
M U X M U X
Capture trigger
T7ICEN
TM7MD2(bp2)
IRQ0 Interrupt request signal IRQ1 Interrupt request signal IRQ2 Interrupt request signal
TM7MD2(bp1-0)
IRQ3 Interrupt request signal
Both edges detection
Capture operation enable / disable
16-Bit capture register
TM7ICL
TM7ICH
TM7IRQ / Synchronous output event
T7PWMSL
TM7MD2(bp6)
SS
Capture register write operation signal
T7ICEDG
Specified edge detection
M U X
M U X
T7ICEDG
TM7MD2(bp7)
Output from the external interrupt interface block
Read
Reserved
Read
Reserved
T7ICT1 T7ICT0
16-Bit binary counter
16-Bit output, compare register 1
16-Bit preset register 2
Synchro- nization
R S
Q