Panasonic MN101C77C - Manual (Page 57)

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Chapter 2 CPU Basics
Overview
2-1-3 Instruction Execution Controller
The instruction execution controller consists of four blocks: memory, instruction queue, instruction regis-
ters, and instruction decoder.
Instructions are fetched in 1-byte units, and temporarily stored in the 2-byte instruction queue. Transfer
is made in 1-byte or half-byte units from the instruction queue to the instruction register to be decoded by
the instruction decoder.
Figure 2-1-2 Instruction Execution Controller Configuration
Instruction decoding
Instruction queue
0
Memory
CPU control signals
Instruction register
7
0 7
Fetch
Instruction decoder
1
byte byte
1 byte or a half byte
0 15