Rockwell Automation 1785-Vx0B, D17856.5.9 PLC-5 VME VMEbus Programmable Controllers User Manual - Manual (Page 109)

Performance and Theory of Operations
Chapter 7
7-4
The benchmark tests that we ran show approximately how long it takes to
perform a ladder-logic message instruction. This means the total elapsed
time from when the enable bit of the instruction went true until the done bit
went true. But the time it takes the data to get to the VMEbus in a write
instruction may actually be a little less than the elapsed time between the
enable and done bits. The reason is that the data actually makes it to the
VMEbus some time before the PLC processor can set the done bit. This is
difficult to measure, but a good estimate would be about 1 msec.
We used the following setup to run the benchmark tests:
The matrix of tests was done in a Motorola development system that
used a MVME 050 system controller card.
One other master board was in the system, but it was not running any
tasks and it was not arbitrating for the VMEbus.
The PLC-5/V40 processor was a series C, revision G processor.
The channels were configured as follows:
Channel: Was configured to:
0 (serial port) system point-to-point (unused)
1A DH+ link
1B a scanner with no racks attached
2A nothing (unused)
2B nothing (unused)
We used the ladder-logic technique to measure the time it takes to perform
a VME transfer. Ladder logic enables a message instruction to do the
VME transfer. Then the ladder logic goes into an endless loop
incrementing a counter every time it goes through the loop. It stays in the
loop until the done bit is set. By knowing the exact time it takes to scan
the logic in the loop, the elapsed time until the done bit is set is calculated
by multiplying the accumulated value of the counter by the time it takes to
scan the loop once. The time it took to scan the following logic in the loop
was 16.1 msec.
MSG
Control MG10:0
MG10:0
EN
CU
JMP
LBL 1
MG10:0
DN
CTU
Counter
Preset
Accum C5:0
32000
0
U
C5:0
MG10:0
EN
MG10:0
DN
Benchmark Tests