Rockwell Automation 1785-Vx0B, D17856.5.9 PLC-5 VME VMEbus Programmable Controllers User Manual - Manual (Page 19)

Chapter 1
Overview
1-8
Table 1.A
Summary of Figure 1.2
In Figure 1.2,
when you see : It means that:
1
Commands are high-level directives sent to the processor from another VMEbus master, typically a
controlling CPU. Commands specific to the VME processor can establish a continuous block copy to/from
the processor and tell the processor to which VMEbus interrupts it should respond. You can also send any
PCCC via this mechanism. PCCCs are commands supported in all 1785 PLC-5 processors. You can use
them to change and modify processor state, for example, or to upload and download memory files.
2
The PLC-5/VME processor responds as a VMEbus slave to certain A16 accesses (to its configuration
registers) and to certain A24 accesses (to its general-purpose memory, if enabled).
3
You can configure the PLC-5/VME processor to respond as an interrupt handler to specified VMEbus
interrupt lines. When one of these interrupts occurs, the processor performs an 8-bit interrupt acknowledge
cycle on the VMEbus to read an 8-bit status/ID from the interrupter. The interrupt and the status/ID value
are then posted for accessibility by the ladder program.
4
The PLC-5/VME processor can perform as a VMEbus interrupter (sender of interrupts) in three
different ways:
•
from a ladder program; the ladder MSG instruction has been extended in the PLC-5/VME processor to
allow a ladder program to generate a VMEbus interrupt.
•
signalling completion of a command (see 7).
•
signalling a completion of each block copy operation for the continuous copy operations (see 8).
5
Another function available via the MSG instruction is VMEbus reads and writes. Rather than just individual
8- or 16-bit accesses, the function allows a block read or write to be done (i.e., of an arbitrary number of
bytes). This is done between a data file in the processor and an arbitrary address range on the VMEbus.
The ladder program can specify the VMEbus address space and data widths to be used.
6
One of the main interfaces of the 6008-LTV processor, and one preserved in the PLC-5/VME processor, is
the ability to predefine two block-copy operations, one into the processor data files and one out of the
processor data files, to be executed automatically every scan loop. These operations are predefined to the
processor via initialization commands from the CPU or from your programming software.
7
The processor can be a VMEbus interrupter signalling completion of a command. This is an option on all
commands and can serve as a way to synchronize the CPU and the processor.
8
The processor can be a VMEbus interrupter signalling completion of each block copy operation for the
continuous copy operations. This is another option that allows the CPU to synchronize with the scan loop
of the processor.
9
Certain standard PCCC commands cause data to be moved into and out of the processor; thus these
commands represent another type of VMEbus interface between the processor and a controlling CPU.
10
The PLC-5/VME processor can be reset with the VME SYSRESET 1 signal. The PLC-5/VME processor
also asserts SYSRESET 1 during power-up initialization until its VMEbus interface hardware is capable of
responding to VMEbus accesses.
11
The PLC-5/VME processor asserts the VME SYSFAIL 1 signal after a reset until the firmware’s self-test
completes successfully. The PLC-5/VME processor makes the state of the VME SYSFAIL 1 signal
available to the ladder program.
12
Assertion of VME ACFAIL 1 causes the processor to halt, with integrity of the ladder program and data files
maintained in the battery-backed memory such that the processor can be restarted upon power up. Your
power supply must assert ACFAIL
1 at least 9ms in advance of the +5VDC supply dropping beneath 4.75V.
13
The PLC-5/VME processor can serve as a VMEbus slot-1 system controller. This enables the PLC-5/VME
processor as a single-level arbiter, a bus timeout timer, and the driver of the VMEbus 16 MHz
SYSCLK signal.
1 indicates a low true signal.