Rockwell Automation 1785-Vx0B, D17856.5.9 PLC-5 VME VMEbus Programmable Controllers User Manual - Manual (Page 39)

3 Chapter
3-1
VMEbus Interface
Read this chapter to understand the basic low-level interface to the
PLC-5/VME processor. The orientation of this chapter is based on a driver
program running on a separate CPU module communicating with
the processor.
Unless otherwise noted, all multiple-byte numerical fields are represented
in big-endian (Motorola) format, meaning that the most-significant data
byte appears in the lowest-addressed byte.
You can configure the PLC-5/VME processor as a VMEbus system
controller by installing it in the left-most slot in the VME chassis. Its
system controller functions are limited, so this mode of operation is
intended for configurations where there is no more-capable CPU in
the system.
As a system controller, a PLC-5/VME processor is a single-level (SGL)
arbiter—it recognizes requests on level 3 only. In this mode, it also
generates the 16 MHz SYSCLK, begins the IACK daisy chain, and has a
bus timer. The bus timer timeouts any VMEbus transaction that asserts a
data strobe (DS0 or DS1) for longer than 93.75-125 microseconds. The
PLC-5/VME processor never asserts BCLR.
When it is not the system controller, you can configure the PLC-5/VME
processor to request the VMEbus on levels 3 or 1.
You select the system controller mode and bus request level by using
a switch (see page 2-3).
Chapter Objectives
System Controller