Zilog Z86193 - Manual (Page 104)

Z8
®
CPU
User Manual
UM001604-0108 Interrupts
97
External Interrupt Sources
External sources involve interrupt request lines IRQ0–IRQ3. IRQ0, IRQ1, and IRQ2 can
be generated by a transition on the corresponding Port 3 pin (P32, P33, and P31 corre-
spond to IRQ0, IRQ1, and IRQ2, respectively).
Figure 92 displays the block diagram for interrupt sources IRQ0, IRQ1, and IRQ2.
The interrupt sources and trigger conditions are device dependent. See the device product
specification to determine available sources (internal and external), triggering edge
options, and exact programming details.
When the Port 3 pin (P31, P32, or P33) transitions, the first flip-flop is set. The next two
flip-flops synchronize the request to the internal clock and delay it by two internal clock
periods. The output of the last flip-flop (IRQ0, IRQ1, or IRQ2) goes to the corresponding
Interrupt Request Register.
Table 18. Interrupt Types, Sources, and Vectors
Name Sources Vector Location Comments
IRQ
0
DAV0, IRQ0, Comparator 0,1 External (P32), Edge Triggered; Internal
IRQ
1
DAV1, IRQ1 2,3 External (P33), Edge Triggered; Internal
IRQ
2
DAV2, IRQ2, T
IN
, Comparator 4,5 External (P31), Edge Triggered; Internal
IRQ3 6,7 External (P30) or (P32), Edge Triggered;
Internal
Serial In 6,7 Internal
T0 8,9 Internal
Serial Out 8,9 Internal
IRQ
5
T1 10,11 Internal
Figure 92. Interrupt Sources IRQ0 – IRQ2 Block Diagram
Note:
P3
n
IRQ
m
System Clock
Multiple Input
n = 2, 3, 1
and Signal
Q S
R
Conditioning
Circuitry
m = 0,1,2
(Internal)
Q D Q D