Power-down modes, Halt mode operation, Stop mode operation – Zilog Z86193 User Manual

Page 117: Halt mode operation stop mode operation

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Z8

®

CPU

User Manual

UM001604-0108

Power-Down Modes

110

Power-Down Modes

In addition to the standard RUN mode, the Z8

®

CPU supports two Power-Down modes to

minimize device current consumption. The two modes supported are HALT and STOP.

Halt Mode Operation

HALT mode suspends instruction execution and turns off the internal CPU clock. The on-
chip oscillator circuit remains active so the internal clock continues to run and is applied to
the Counter/Timer(s) and interrupt logic.

To enter HALT mode, it is necessary to first flush the instruction pipeline to avoid sus-
pending execution in mid-instruction. To do this, the application program must execute a
NOP instruction (opcode =

FFh

) immediately before the HALT instruction (opcode

7Fh

),

that is:

FF NOP ;clear the instruction pipeline

7F HALT ;enter HALT mode

HALT mode is exited by interrupts, either externally or internally generated. Upon com-
pletion of the interrupt service routine, the user program continues from the instruction
after HALT.

HALT mode may also be exited via a POR/RESET activation or a Watch–Dog Timer
(WDT) time-out. (See the product data sheet for WDT availability). In this case, program
execution restarts at the reset restart address

000Ch

.

To further reduce power consumption in HALT mode, some Z8 family devices allow
dynamic internal clock scaling. Clock scaling may be accomplished on the fly by repro-
gramming bit 0 and/or bit1 of the Stop Mode Recovery register. See

Figure 103

on page

112.

Internal clock scaling directly affects Counter/Timer operation—adjustment of the pres-
caler and downcounter values may be required. To determine the actual HALT mode cur-
rent (I

CC1

) value for the various optional modes available, see the related Z8

device’s

product specification.

Stop Mode Operation

STOP mode provides the lowest possible device standby current. This instruction turns
OFF the on-chip oscillator and internal system clock.

To enter STOP mode, it is necessary to first flush the instruction pipeline to avoid sus-
pending execution in mid-instruction. To do this, the application program must execute a

Note:

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