Zilog Z86193 - Manual (Page 241)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
234
Subtract
Syntax
SUB dst, src
Instruction Format
Operation
dst
←
dst–src
The source operand is subtracted from the destination operand and the result is stored in
the destination operand. The contents of the source operand are not affected. Subtraction is
performed by adding the two’s complement of the source operand to the destination oper-
and.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding
1110b
(
Eh
) to the
high nibble of the operand. For example, if Working Register
R12 (CH)
is the destination
operand, then
ECh
is used as the destination operand in the Op Code.
Cycles
OPC
(Hex)
Address
Mode
dst src
OPC dst src
6 22 r r
6 23 r lr
OPC src dst
10 24 R R
10 25 R IR
OPC dst src
10 26 R IM
10 27 IR IM
Flag Description
C
Cleared if there is a carry from the most significant bit of the result; set otherwise,
indicating a borrow.
Z Set if the result is 0; cleared otherwise.
V Set if arithmetic overflow occurred (if the operands were of opposite sign and the
sign of the result is the same as the sign of the source); reset otherwise.
S Set if the result is negative; cleared otherwise.
H Cleared if there is a carry from the most significant bit of the low order four bits of
the result; set otherwise indicating a borrow.
D Always set to 1.
E src or E dst
Note: