Reset conditions – Zilog Z86193 User Manual

Page 116

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Z8

®

CPU

User Manual

UM001604-0108

Interrupts

109

EI ;Enable interrupt mechanism

DI ;Disable vectored interrupts.

To initiate polled processing, check the bits of interest in the IRQ using the Test Under
Mask (TM) instruction. If the bit is set, call or branch to the service routine. The service
routine services the request, resets its Request Bit in the IRQ, and branches or returns back
to the main program. An example of a polling routine is as follows:

In this example, if IRQ2 is being polled, MASKA is

00000100b

and MASKB is

11111011b

.

Reset Conditions

Upon reset, all bits in IPR are undefined.

In IMR, bit 7 is 0 and bits 0–6 are undefined. The IRQ register is reset and held in that
state until an enable interrupt (EI) instruction is executed.

TM IRQ, #MASKA

;Test for request

JR Z, NEXT

;If no request go to NEXT

CALL SERVICE

;If request is there, then

;service it

NEXT:

.

.

.

SERVICE:

;Process Request

.

.

.

AND IRQ, #MASKB ;Clear Request Bit

RET

;Return to next

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