Zilog Z86193 - Manual (Page 118)

Z8
®
CPU
User Manual
UM001604-0108 Power-Down Modes
111
NOP instruction (opcode =
FFh
) immediately before the STOP instruction
(opcode =
6Fh
), that is,
FF NOP ;clear the instruction pipeline
6F STOP ;enter STOP mode
STOP mode is exited by any one of the following resets: POR activation, WDT time out
(if available), or a Stop Mode Recovery source. Upon reset generation, the processor
always restarts the application program at address
000Ch
.
POR/RESET activation is present on all Z8 devices and is implemented as a reset pin and/
or an on-chip power on reset circuit.
Some Z8 devices allow for the on-chip WDT to run in STOP mode. If so activated, the
WDT time-out generates a reset some fixed time period after entering STOP mode.
Stop Mode Recovery by the WDT increases STOP mode standby current (I
CC2
). This is
due to the WDT clock and divider circuitry that is now enabled and running to support this
recovery mode. See the product data sheet for actual I
CC2
values.
All Z8 devices provide some form of dedicated Stop Mode Recovery circuitry. Two SMR
methods are implemented—a single fixed input pin or a flexible, programmable set of
inputs. The selected Z8 device product specification should be reviewed to determine the
SMR options available for use.
For devices that support SPI, the slave mode compare feature also serves as a SMR source.
In the simple case, a low level applied to input pin P27 triggers a SMR. To use this mode,
pin P27 (I/O Port 2, bit 7) must be configured as an input before STOP mode is entered.
The low level on P27 must meet a minimum pulse width T
WSM
. (See the product data
sheet) to trigger the device reset mode). Some Z8 devices provide multiple SMR input
sources. The appropriate SMR source is selected via the SMR Register.
Use of specialized SMR modes (P2.7 input or SMR register based) or the WDT time-out
(only when in STOP mode) provide a unique reset operation. Some control registers are
initialized differently for a SMR/WDT triggered POR than a standard reset operation. See
the product specification (register file map) for exact details.
To determine the actual STOP mode current (I
CC2
) value for the optional SMR modes
available, see the selected Z8 device’s product data sheet.
STOP mode current (I
CC2
) is minimized when:
•
V
CC
is at the low end of the devices operating range
•
WDT is off in STOP mode
•
Output current sourcing is minimized
•
All inputs (digital and analog) are at the low or high rail voltages