Zilog Z86193 - Manual (Page 122)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
115
Serial Input/Output
UART Introduction
Some Z8
®
CPU microcontrollers contain an on-board full-duplex Universal Asynchro-
nous Receiver/Transmitter (UART) for data communications. The UART consists of a
serial input/output (SIO) Register located at address
F0h
, and its associated control logic
(see Figure 105 ). The SIO is actually two registers, the receiver buffer and the transmitter
buffer, which are used in conjunction with Counter/Timer T0 and Port 3 I/O lines P30
(input) and P37 (output). Counter/Timer T0 provides the clock input for control of the data
rates.
Configuration of the UART is controlled by the Port 3 Mode (P3M) Register located at
address
F7h
. Z8
®
CPU always transmits eight bits between the start and stop bits (eight
Data Bits or seven Data Bits and one Parity Bit). Odd parity generation and detection is
supported.
The SIO Register and its associated Mode Control Registers are mapped into the Standard
Z8 Register File as listed in
Table 23 on page 116. The organization allows the software to
access the UART as general-purpose registers, eliminating the requirement for special
instructions.
Figure 105. UART Block Diagram
Stop
Bit Detect
Transmitter
Shift Register
÷
6
Parity
Gan
Serial
Out Char
Detect
Receiver
Buffer
Receiver
Shift Register
Serial
In
Start
Bit Detect
Clock
Control
Parity
Check
Shift
Clock
Shift
Clock
÷
16
Transfer
Stop
Start
Write FOH
RESET
Read FOH
Mark
Serial I/O Clock (From T0)
IRQ
4
Internal Data Bus
IRQ
3
P3
7 P3
0