Zilog Z86193 - Manual (Page 130)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
123
Mode Recovery, Master/Slave selection, and Compare mode. Table 25 contains the pin
configuration for the SPI feature when it is enabled. The SPI consists of four registers: SPI
Control Register (SCON), SPI Compare Register (SCOMP), SPI Receive/Buffer Register
(RxBUF), and SPI Shift Register. SCON is located in bank (C) of the Expanded Register
File at address 02.
The SPI Control Register (SCON; see Figure 116 on page 124), is a read/write register
that controls Master/Slave selection, interrupts, clock source and phase selection, and
error flag. Bit 0 enables/disables the SPI with the default being SPI disabled. A 1 in this
location enables the SPI, and a 0 disables the SPI. Bits 1 and 2 of the SCON register in
Master Mode select the clock rate. You can choose whether internal clock is divide-by-2,
4, 8, or 16. In Slave Mode, Bit 1 of this register flags the user if an overrun of the RxBUF
Register has occurred. The RxCharOverrun flag is only reset by writing a 0 to this bit. In
slave mode, bit 2 of the Control Register disables the data-out I/O function. If a 1 is writ-
ten to this bit, the data-out pin is released to its original port configuration. If a 0 is written
to this bit, the SPI shifts out one bit for each bit received. Bit 3 of the SCON Register
enables the compare feature of the SPI, with the default being disabled. When the compare
feature is enabled, a comparison of the value in the SCOMP Register is made with the
value in the RxBUF Register. Bit 4 signals that a receive character is available in the
RxBUF Register.
Table 25. SPI Pin Configuration
Name Function Pin Location
DI Data-In P20
DO Data-Out P27
SS Slave Select P35
SK SPI Clock P34