Zilog Z86193 - Manual (Page 211)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
204
Logical AND
Syntax
AND dst, src
Instruction Format
Operation
dst
←
dst AND src
The source operand is logically ANDed with the destination operand. The AND operation
results in a 1 being stored whenever the corresponding bits in the two operands are both 1,
otherwise a 0 is stored. The result is stored in the destination operand. The contents of the
source bit are not affected.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding
1110b
(
Eh
) to the
high nibble of the operand. For example, if Working Register R12 (CH) is the destination
operand, then
ECh
is used as the destination operand in the Op Code.
Cycles
OPC
(Hex)
Address
Mode
dst src
OPC dst src
6 42 r r
6 43 r lr
OPC src dst
10 44 R R
10 45 R IR
OPC dst src
10 46 R IM
10 47 IR IM
Flag Description
C Unaffected
Z Set if the result is zero; cleared otherwise
S Set if the result of bit 7 is set; cleared otherwise
V Always reset to 0
D Unaffected
H Unaffected
E src or E dst
Note: