Zilog Z86193 - Manual (Page 126)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
119
After a full character has been assembled in the receiver’s buffer, SIO Register (
F0h
),
Interrupt Request IRQ3 is generated. The shift clock is stopped and the Shift Register reset
to all 1s. The start bit detection circuitry begins monitoring the data input for the next start
bit. This cycle allows the receiver to synchronize on the center of the bit time for each
incoming character.
Overwrites
Although the receiver is single buffered, it is not protected from being overwritten, so the
software must read the SIO Register (
F0h
) within one character time after the interrupt
request (IRQ3). Z8
®
CPU does not have a flag to indicate this overrun condition. If poll-
ing is used, the IRQ3 bit in the Interrupt Request Register must be reset by software.
Framing Errors
Framing error detection is not supported by the receiver hardware, but by responding to
the interrupt request within one character bit time, the software can test for a stop bit on
P30. Port 3 bits are always readable, which facilitates break detection. For example, if a
null character is received, testing P30 results in a 0 being read.
Parity
The data format supported by the receiver must have a start bit, eight data bits, and at least
one stop bit. If parity is on, bit 7 of the data received will be replaced by a Parity Error
Flag. A parity error sets bit 7 to 1, otherwise, bit D7 is set to 0.
Figure 111 on page 120 dis-
plays these data formats.
Figure 110. Receiver Timing
Shift register Contents
(R)
Shift
RCVR
Start Bit Transition Detected
Eight T0 Counts Later Shifting Starts
Stop Bit
One or More
Transferred to Receive Buffer
and IRQ3 is Generated
RCVR
Data
Clock
IRQ3